IEEE

Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing

Abstract: Most Wearable Ultrasound (WUS) devices lack the computational power to process signals at the edge, instead relying on remote offload, which introduces latency, high power consumption, and ...
University of Vermont

RISC vs CISC

RISC (reduced instruction set computer), and CISC (complex instruction set computer). These two principles govern fundamental choices of CPU design and implementation. RISC architectures, such as ARM, ...
IEEE

Enhancing Computer Architecture Education Through Decentralized Visual Programming and RISC-V Simulation

Abstract: Teaching computer architecture and assembly language poses significant challenges due to the complexity of underlying concepts and the technical barriers associated with traditional ...
Digi Times

Arm beats Intel and AMD in DPUs; can RISC-V reshape competition?

Data centers are often seen as battlegrounds among the three major CPU architectures (x86, Arm, RISC-V) and GPUs from Nvidia, AMD, and specialized ASIC vendors. The Arm architecture has already ...