Hackaday

2025 Component Abuse Challenge: Digital Logic With Analog Components

Tim] noticed recently that a large number of projects recreating discrete logic tend to do so with technology around 70 years ...
Semiconductor Engineering

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)

FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage” was published by researchers at Nanyang Technological ...

When Logic Meets Design: Empowering Left-Brain Teams With Right-Brain Results

Business culture has long suggested that only "designers" or "creatives" should own visual communication. But with the right ...
IEEE

Fully Programmatic Automated Design Procedure of Comparators for Analog-to-Digital Converters

Abstract: This article proposes a system-aware, fully programmatic and automated, process agnostic design methodology, which utilizes system-level simulations with the layout parasitics of the circuit ...
IEEE

Digital-to-Time Converter and Its Application to Fractional-N Frequency Synthesis: Circuits from a Systems Perspective

Abstract: This article provides a tutorial on digital-to-time converters (DTC), which are the core blocks of many electronic applications. Common DTC circuit topologies and major DTC timing errors are ...