IEEE

Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms

Abstract: Multi-valued logic (MVL) circuits, especially the ternary logic circuits, have attracted great attention in recent years due to their higher information density than binary logic systems.
IEEE

An Efficient Power Optimization Approach for Fixed Polarity Reed–Muller Logic Circuits Based on Metaheuristic Optimization Algorithm

Abstract: With the emergence of the multicore architecture and the increase of chip operating frequency, power optimization has become a key step of circuit logic synthesis. Aiming at the XNOR/OR ...
GitHub

using torch.sym_not cause Z3Exception: Symbolic expressions cannot be cast to concrete Boolean values.

PYTORCH_TEST_WITH_ASAN=1 PYTORCH_TEST_WITH_UBSAN=1 python test/dynamo/test_dynamic_shapes.py DynamicShapesReproTests.test_issue175_dynamic_shapes File "/home/lsakka ...
GitHub

Java OpenCL Logic Circuit Simulator

Java OpenCL Logic Circuit Simulator for simulating and debugging fully pipelined binary gate logic. Includes visual designer that also converts OpenCL C code to binary micro-fpga gate logic. Not ...