Semiconductor Engineering

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)

FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage” was published by researchers at Nanyang Technological ...
IEEE

Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing

Abstract: A memristive stateful logic circuit can provide a non-von Neumann computing architecture for integrating computation and storage. However, the stateful logic circuit based on memristors ...