GitHub

CMOS XOR Gate Design – Cadence Virtuoso

The following schematic shows the CMOS implementation of a 2-input XOR gate using complementary pull-up and pull-down networks: Figure: CMOS XOR gate schematic drawn in Cadence Virtuoso. Input A: ...
GitHub

JK Flip-Flop Using NAND Gates

This project is a gate-level implementation of a JK flip-flop using only NAND gates, built and simulated in Logisim Evolution (v3.7.2). The idea was to understand how the JK flip-flop works internally ...
IEEE

BAM-Net: Hardware Friendly Associative Memory Using Binary Dominant Weights and NAND Logic

Abstract: This paper presents BAM-Net, a hardware-efficient binarization algorithm designed for associative memory (AM) implementation. BAM-Net aims to reduce memory overhead, power consumption, and ...
IEEE

Design and Evaluation of Low Power 2 to 4 Decoder Circuit Using Three and Four Transistors NAND Gates

Abstract: This paper presents a new design of a 2 to 4 decoder constructed using 3-transistor NAND gates, contrasting it with the conventional 4 transistor NAND gate-based technique. The primary aim ...
Mississippi Valley Publishing

Iowa company finds use for discarded wind turbine blades

Three wind turbine blades sit ground up inside the concrete blocks of a new retaining wall at Premier Credit Union in downtown Des Moines. It’s the latest project from Renewablade, a company in ...