Researchers argue that 'at least 40%' of the bloated x86 ISA could be removed and emulated to improve CPU efficiency

The researchers "conclude that at least 40% of the x86 ISA, even after excluding multimedia extensions, could be emulated ...
WV News

New AI-native processor for edge applications offers 100x power and performance improvements over 32-bit MCUs

Unique chip architecture of new GPX10 Pro from Ambient Scientific features 10 programmable AI cores which implement a custom ...
Semiconductor Engineering

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.)

A new technical paper titled “Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions” was published by researchers at Tampere University. Abstract “Custom instruction ...
IEEE

A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture

Abstract: Different modes of convolution, as the main operations of convolutional neural networks, determine the efficiency of the entire network. This paper proposes a multi-mode convolution ...
IEEE

Invited Paper: Instruction Set Extensions for Post-Quantum Cryptography

Abstract: Quantum computing is one of the latest break-throughs in the field of computer science, having the potential of breaking the underlying assumptions of public-key cryptography. With the ...