IEEE

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency

Abstract: Large Language Models (LLMs) have demonstrated promising capabilities in generating Verilog code from module specifications. To improve the quality of such generated Verilog codes, previous ...
IEEE

AMBA AHB to APB Bridge Protocol Verification Using System Verilog

Abstract: The AHB (Advanced High-performance Bus) is a member of the AMBA (Advanced Microcontroller Bus Architecture) bus family and is a high-performance, low-power, high-bandwidth bus. It serves as ...