IEEE

Review of Simulation Methods for Design of Spin Logic

Abstract: While the scaling of CMOS electronics continues and reaches the sub-10 nanometer range, active research is being conducted on logic devices beyond CMOS to find a path to a more energy ...
IEEE

Using Mixed Logic Synthesis Tools in Open-Source FPGA Design Framework

Abstract: In recent years, several open-source logic synthesis tools and design frameworks have emerged. However, there is limited research on the interactive combinations of these logic synthesis ...