IEEE

FPGA Implementation of Sparse Matrix Vector Multiplication with Small-Scale Matrix Element Router

Abstract: Sparse Matrix Vector multiplication (SpMV) is a fundamental operation in various computational science applications, characterized by a significant degree of inherent parallelism. Recent ...
Business Wire

SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center

SANTA CLARA, Calif.--(BUSINESS WIRE)--Further expanding SiFive’s lead in RISC-V AI IP, the company today launched its 2nd Generation Intelligence™ family, featuring five new RISC-V-based products ...
The Daily News

SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center

Further expanding SiFive’s lead in RISC-V AI IP, the company today launched its 2nd Generation Intelligence™ family, featuring five new RISC-V-based products designed to accelerate AI workloads across ...
Morningstar

SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center

SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center New X100 Series Joins Upgraded X200, X300 and XM IP to Address Growing ...
IEEE

Design and Evaluation of a Virtual Vector Based Modulated Model Predictive Control for the Indirect Matrix Converters With Improved Performance

Abstract: A virtual vector based modulated model predictive control (VV-M2PC) strategy is proposed for the indirect matrix converters (IMCs) in this article. Compared with the conventional M2PC, the ...