EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
EDN

Generate FPGA designs from M-code

DSP systems are best described by using a combination of both graphical-and language-based methods. The MathWorks, an industry leader in DSP modeling software, caters to this dichotomy by providing a ...
AOL

Avnet Electronics Marketing Americas Announces a New Development Kit Featuring MATLAB® and Simulink®

BOSTON & PHOENIX--(BUSINESS WIRE)-- Avnet Electronics Marketing Americas, a business region of Avnet, Inc. (NYSE: AVT), and MathWorks, the leading developer of mathematical computing software, today ...
Electronics Weekly

FPGA toolkit has IEEE754 floating point libraries

Celoxica has available a toolkit for floating-point arithmetic implementation in high-density programmable logic. The IEEE 754 compliant libraries support single, double and custom precision ...
Design-Reuse

Altera First to Benchmark Complex High-Performance Floating-Point Digital Signal Processing Designs on 28 nm FPGAs

Altera’s DSP Builder Advanced Blockset™ Design Flow Verified by BDTI, the Industry's Most Trusted Source of Independent DSP Technology Analysis San Jose, Calif., October 29, 2012— Altera ...