IEEE

A Multi-Expert Large Language Model Architecture for Verilog Code Generation

Abstract: Recently, there has been a surging interest in using large language models (LLMs) for Verilog code generation. However, the existing approaches are limited in terms of the quality of the ...
IEEE

Automatic Generation of System Verilog Assertions for Verification of Safety Mechanisms

Abstract: The prevalence of safety-critical applications has increased, resulting in a heightened demand for designs that prioritize functional safety. These designs are characterized by the inclusion ...
GitHub

context free promotion of array indices to int triggers WIDTHTRUNC warnings from verilator as array indices are short (or less)

This really can only be solved by passing the context down into the compilation of (system) verilog, as the problem is the context-free interpretation of array indices as int-length (32 or 64 bit) ...
GitHub

Smart Error Code Generator

Find the location of the error code in the project. the format shuld be given in {path}{line}. (line optional) note that the relative path and code generation ...