Stacking dies will dramatically improve performance, but it’s still a work in progress.

Open-source tools and multi-project wafer (MPW) shuttles democratize chip design for low cost. Small circuits, both analog and digital, are accommodated by embedding them as “tiles” or “clusters” into ...

Chip design is starting to include more options to ensure chips behave reliably in the field, boosting the ability to tweak both hardware and software as chips age. The basic problem is that as ...

AI and data center chips are hitting limits. A new 3D chip design improves speed, power use and memory bandwidth.

The backside of the wafer refers to the opposite surface of the silicon wafer from where the transistors and circuits are ...

Launching a pilot 'chip design to tapeout' flow curriculum, enabling academic institutions with industry-aligned coursework. Pilot testing underway at over 40 select worldwide universities with intent ...

From left to right: UT Ph.D. student Song Hang Chai, post-doctoral researcher Hyunsu Chae, professor David Pan and assistant professor Sensen Li. Radio frequency integrated circuits (RFIC) are ...

Cadence Design Systems is a mission-critical enabler of next-gen industries, boasting high recurring revenues, robust client retention, and an AI-driven product portfolio. The company’s oligopolistic ...

SNPS expands its TSMC partnership, advancing AI, SoC, and multi-die design with certified flows, IP, and 3DIC innovations.

Like any successful system-on-chip (SoC) effort, a multi-die system-in-package (SiP) project must start with a sound system design. But then what? Are the steps in the SiP design flow different from ...

Cambridge GaN Devices (CGD) has entered a manufacturing partnership with GlobalFoundries (GF) to produce its ICeGaN power ...