EDN

Synopsys ‘pioneers’ SystemVerilog testbench tool

SANTA CRUZ, Calif. — Synopsys Inc. is bringing the “ecosystem” built around its VCS Verilog simulator to users of third-party simulators with Pioneer-NTB, a SystemVerilog testbench automation tool ...
EDN

Synopsys announces SystemVerilog testbench

At the SNUG (Synopsys Users Group) East meeting this week in Boston, Synopsys will release Pioneer-NTB, its new automatic testbench-verification system supporting the SystemVerilog design and ...
Design-Reuse

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
New Electronics

Structured messages ease SystemVerilog testbench debug

In the latest release of its Verdi automated debug system, eda specialist SpringSoft has it is providing 'comprehensive SystemVerilog Testbench (SVTB) debug support'. Fully integrated with the company ...
Hackaday

FPGA Testbenches Made Easier

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

SystemVerilog marries a number of verification concepts, primarily in the areas of design, assertions, and testbench creation, that were previously embodied in separate and sometimes proprietary ...
Electronic Design

SystemVerilog: The Complete Solution

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a ...