Semiconductor Engineering

RTL Design-for-Power (DFP) Methodology

Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level ...
Design-Reuse

Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach

In today’s fast-paced silicon industry, hardware design is under constant pressure to innovate, iterate, and ship faster. Traditional Register Transfer Level (RTL) design processes—though foundational ...

Si2 Names NVIDIA, Synopsys Technologists to Lead New LLM Benchmarking Coalition

Si2 announces the chair and vice chair of the Si2 LLM Benchmarking Coalition, an industry initiative advancing AI for silicon ...
Electronic Design

Verification Techniques For FPGA Designs

With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...
Design-Reuse

Tensilica Announces Major IC Design Automation Breakthrough: The Automatic Generation of Optimized Programmable RTL Engines from Standard C Code

SANTA CLARA, Calif. – July 7, 2004 - Tensilica, Inc. today announced that it has achieved a major design automation breakthrough – the automated design of optimized configurable processors from ...