Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
EDN

DDR3 memory interface controller IP speeds data processing applications

DDR3 memory systems can provide a significant performance boost to a variety of data processing applications. However, compared to previous generations (DDR and DDR2), DDR3 memory devices have some ...
Business Wire

Rambus Expands Portfolio of DDR5 Memory Interface Chips for Data Centers and PCs

SAN JOSE, Calif.--(BUSINESS WIRE)--Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the expansion of its DDR5 memory interface chip ...
Business Wire

JEDEC® Announces Updates to Universal Flash Storage (UFS) and Memory Interface Standards

ARLINGTON, Va.--(BUSINESS WIRE)--JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of ...
Electronic Design

Leverage High-Frequency Source-Synchronous Memory in SoC Design

Download this article in PDF format. Today’s embedded systems require high external memory bandwidth to achieve fast boot time and application loading time with minimal cost. Historically, ...