Gaps in the memory hierarchy have created openings for new types of memory, and there is no shortage of possibilities. It’s no secret that today’s memory chips and storage devices are struggling to ...

The announcement this week by Intel and Micron Technology of 3D XPoint memory, which will sit somewhere between DRAM and NAND flash in future systems, has everyone thinking about the architectural, ...

These are exciting times for the memory hierarchy in systems. New kinds of DRAM and non-volatile memories are becoming available to system architects to enhance the performance and responsiveness of ...

The dynamic interplay between processor speed and memory access times has rendered cache performance a critical determinant of computing efficiency. As modern systems increasingly rely on hierarchical ...

New non-volatile memory devices store information using different physical mechanisms from those employed in today's memories and could achieve substantial improvements in computing performance and ...

It is something we all experience. We learn something, but then forget it as soon as we turn away. In the late 19th century, ...

TOKYO--(BUSINESS WIRE)--Kioxia Corporation, a world leader in memory solutions, today announced that the company’s research papers have been accepted for presentation at IEEE International Electron ...

Semiconductor Engineering sat down to discuss future memory with Frank Ferro, senior director of product management for memory and interface IP at Rambus; Marc Greenberg, director of product marketing ...

One of the greatest challenges facing the designers of many-core processors is resource contention. The chart below visually lays out the problem of resource contention, but for most of us the idea is ...

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To ...