Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
TechRepublic

Verification of Asynchronous FIFO Using System Verilog

FIFO (First In First Out) is a buffer that stores data in a way that data stored first comes out of the buffer first. Asynchronous FIFO is most widely used in the System-on-Chip (SoC) designs for data ...
EDN

Mixed-mode verification of DDR, LCD, and memory sub-systems: Verilog-AMS vs. SPICE

Editor's note: This paper is the third in a series covering the pros and cons of using a Verilog-AMS view with respect to a SPICE view for verification of SOC IP having an analog component. The first ...
Design-Reuse

NextOp Announces BugScope Assertion Synthesis for Progressive, Targeted Verification

SANTA CLARA, Calif., May 6, 2010 -- NextOp Software, Inc. today announced BugScope, the industry’s first assertion synthesis product to synthesize high quality assertions and functional coverage ...
mccormick.northwestern.edu

COMP_ENG 387: Real-Time Digital Systems Design and Verification with FPGAs

**Graduate students interested in taking this course for Winter 2024 should enroll in COMP_ENG 495: Real-Time Digital Systems Design and Verification with FPGAs to get graduate credit. Class ...