SAN MATEO, Calif. Synopsys Inc. hopes to hold on to a slight lead in the formal verification market as it moves customers from the Design Verifyer tool to its internally developed Formality ...

Synopsys gives equivalency checker a new look By Richard Goering, EE Times March 18, 2002 (12:20 p.m. EST) URL: http://www.eetimes.com/story/OEG20020318S0028 MOUNTAIN ...

Logic Equivalence Check, popularly known as LEC is one of the most important parts of the ASIC VLSI design. Formal verification techniques have been developed using mathematical proof rather than ...

Time-saving verification tools have been added to an advanced tool flow for high-end FPGA design. The flow, a collaboration between Xilinx Inc. of San Jose and Synopsys Inc. of Mountain View, Calif., ...

MOUNTAIN VIEW, Calif. — In an effort to make formal equivalency checking more accessible to designers who aren't formal-verification experts, Synopsys Inc. this week will roll out a “flow-based” user ...